What is the targetted market for this Chip.

What are the competitor's to this Chip and Market Requirement and ROI

What is the Fabrication Unit the Chip is targetted for?

What is the Success rate and Yield numbers achieved in the Fabrication Unit

What is the technology Process targetted for

What is the correlation of the library models w.r.t. Silicon

What are the various Protocols the Chip is going to address

Hardware & Software Parti-tioning.

What is the processor/micro-controller suitable for this application.

What is the bus-architecture targetted

What is the performance targets for this bus architecture

What are the various Interfaces the Chip is having

Is the design going to be in single Vt or with Multi-Vt design

Is using Embedded macro's right choice or Memory Macros

What are the IP's are going to be Re-usued

What are the IP's going to Hard-macro's

What is the Verification Status and corner-case coverage of the I.P's

What is the Die-size targetted/Estimated for the Chip

What is the Power targets

Is Power Management Unit a requirement in the chip to reduce Dynamic power

What are the mechanisms followed to reduce the leakage power

Is Module enables/clock-gating a part of the Methodology

Is resets going to synchronous or asynchronous

What are the various Synchronous Mechanisms for data-transfer's

How many clock-domains required for the Chip

How many PLL's are required or single PLL sufficient for all the clocks required

What is the thought process behind PAD's Is LVTTL/SSTL pads

Is the package going to wire-bond or Flip-chip

Methodology for Optimal Power-grid design

What are the noise reducing Mechanism's in case of analog integration

Is there any requirement of speed monitor's or process checking blocks

What is the type of fuses used laser fuse or efuses

Is there any requirement of Fib Cells in the Design

What are the mechanism's used to handle ESD

what is the reliability target of the Chip and how it is addressed

What are the Mechanisms used for Yield improvement

Is the chip tested at at-speed test

How much Memory-map is allocated for the IP's

What is the metric for spare-gates in the Chip for ECO's

Is repairable memories required

What is the tester targetted and the requirement to the Chip in terms of Scan-chain

Is test-vector compression mechanism's a requirement

What is the PLL performance in terms of Jitter

What is the Interrupt handling mechanism with in the Chip.

What is the ROM-Code for the Chip.

What is the Chip utilization targets

Will the chip be routable or any requirement for special libraries with different routing tracks.

What is the Methodology for tools and versions

What is the Version control mechanism planned for data handling across multi Geographical Environments.

What is the signoff criteria for the Chip

What is the frequency targets for the Chip.

Is there room for further revisions of the Chip.

If the Chip has DDR/SDR interface is there any requirement for DLL.

What are the limitations of the Tools interms of Complexity/run-times/turn-around times/Computation Power requirements.

What is the Mechanisms/Steps taken for the various Variabilities in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.

About the Author:

Author is a Chip Design Veteran, provides News/Jobs/Views/Blogs/Forums/Discussions about Semiconductor, Wafer Processing, Lithography, Meterology, Semiconductor/Design/EDA Companies, Clean Rooms, Etching[Wet/Dry], EDA Tools, Product Informations, VLSI Chip Design Flow, Chip Design Concepts, Chip Design Issues/solutions from Silicon2Systems all in one-place. Visit http://www.vlsichipdesign.com

Article Source: ArticlesBase.com - Thoughts of a Good Chip Design Architect